Integrated circuits comprising devices with node widths of less than 32 nm typically utilize a combination of high dielectric constant (high k) material and metal to form gate structures for metal oxide semiconductor (MOS) devices. There are two primary approaches to fabricating high k-metal gate structures (referred to as a high k stack) on a semiconductor substrate: a gate first approach and a gate last approach. A gate first approach uses a single deposition step for depositing one type of work function metal to form the high k stack for a single type of device, either PMOS or NMOS. Using a gate last approach, both PMOS and NMOS devices can be created on the same substrate. As such, metals having two different work functions are deposited to respectively form the PMOS and NMOS gate structures in a single integrated circuit.
To utilize a gate last approach, after high k dielectric deposition, polysilicon is deposited across the substrate, then masked and etched to form a polysilicon cap to protect the dielectric while other process steps are completed. Subsequently, the polysilicon is removed (etched) from the high k stack of a first type device (e.g., PMOS device), while the high k stack of a second type device (e.g., NMOS device) is masked. A metal having a particular work function (e.g., titanium nitride (TiN)) for producing a P-type device is deposited on top of the high k dielectric of the PMOS device. The gate structure is completed by filling a contact via with aluminum to form a conductive path to the metal. The substrate is then polished using a chemical mechanical polishing (CMP) system to planarize the aluminum at the top of the high k stack and remove the mask.
Removal of the mask from the high k stack of the NMOS device exposes the polysilicon atop the high k dielectric of the NMOS device. The polysilicon is removed (e.g., etched) to expose the high k dielectric. A metal having a particular work function (e.g., titanium aluminum nitride (TiAlN)) for producing an N-type device is deposited on top of the high k dielectric of the NMOS device. Filling a contact via with aluminum to form a conductive path to the metal completes the gate structure. The substrate is then polished using a chemical mechanical polishing (CMP) system to planarize the metal at the top of the high k stack.
Simultaneously with creating the PMOS device, MOS capacitors are also fabricated. The MOS capacitors are formed in the same manner as a PMOS device, except the drain and source are connected to one another to form a first electrode (bottom electrode) of the capacitor and the gate metal forms a second electrode (top electrode) of the capacitor. These capacitors have very large surface area metallization compared to the width of the gate metallization.
When this procedure is followed, the contact metal (e.g., aluminum) of the PMOS high k stack and the MOS capacitors is polished twice and may incur substantial dishing. The dishing may be so severe that the gate metal is exposed and the threshold voltage of the PMOS device is significantly altered. The result may be an inoperative PMOS device.
Additionally, the size of the metalized surface area of the capacitors also results in dishing. Such dishing occurs whether the capacitor is polished once or twice. Thus, a dishing problem may be experienced in a gate first approach or if the capacitors were formed simultaneously with the NMOS devices in a gate last approach.
Therefore, there is a need in the art for a method and integrated circuit structure for mitigating metal gate dishing.
SUMMARY
A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing are described. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; and a third area comprising at least one capacitor having an uppermost layer of polysilicon, wherein the capacitor area is greater than a sum of the first and second areas. The third area is distributed among the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
According to another embodiment, an integrated circuit structure includes at least one first type device comprising a first metal electrode; at least one second type device comprising a second metal electrode; and at least one capacitor comprising a polysilicon layer to enable uniform polishing of the first and second metal electrodes. The at least one capacitor is distributed among the first and second type devices.
According to yet another embodiment, a method of forming an integrated circuit includes forming a first high k gate stack for at least one first type device, wherein the first high k gate stack has a first surface area; forming a second high k gate stack for at least one second type device, wherein the second high k gate stack has a second surface area; and forming a polysilicon cap upon at least one capacitor, wherein the polysilicon cap has a third surface area. The third surface area is larger than a combined surface area of the first surface area and second surface area. The third surface area is distributed among the first and second surface areas.